(herald (assembler ppc_misc)
  (env t
       (assembler as_open)
       (assembler ppc_machine)
       (assembler ppc_format))
  (syntax-table tas-ppc-syntax-table))

;;;; PowerPC Instruction Set: Miscellaneous Instructions

;;; Copyright (C) 2006, Taylor Campbell.
;;; All rights reserved.
;;; See the LICENCE file for details.

;;; Syscall

(let ((sc-fg (fg-template (ppc/sc)
               (printer "sc")
               (fields (fixed 5 #b010001)
                       (0 0 0 0 0)
                       (0 0 0 0 0)
                       (0 0 0 0) (0 0 0 0) (0 0 0 0) (0 0)
                       (1) (0)))))
  (define-ppc-op (sc) (sc-fg)))

;;; Enforce In-order Execution of I/O

(define-nullary-ppc-op eieio #b1101010110)

;;; Instruction Cache Block Invalidate

(define-ppc-op (icbi rA rB)
  (ppc/arith-format ppc-reg/zero rA rB
                    #b011111 #b1111000010
                    (lambda (port rD rA rB)
                      (ignore rD)
                      (format port "icbi ~A,~A" rA rB))))

;;; Instruction Synchronize

(define-nullary-ppc-op isync #b0010010110)

;;;; Special-Purpose Register Movement

;;; Move Condition Register Field

(define-ppc-op (mcrf crfD crfS)
  (ppc/spr-move #b010011
                (assemble-fixnum (fx 3 crfD) (0 0))
                (assemble-fixnum (fx 3 crfS) (0 0))
                0
                #b0000000000 0
                (lambda (port) (format port "mcrf ~D,~D" crfD crfS))))

;;; Move to Condition Register from FPSCR

(define-ppc-op (mcrfs crfD fpscrfS)     ;fpscrfS = FP Status & Control
  (ppc/spr-move #b111111                ; Register Field Source
                (assemble-fixnum (fx 3    crfD) (0 0))
                (assemble-fixnum (fx 3 fpscrfS) (0 0))
                0
                #b0001000000 0
                (lambda (port)
                  (format port "mcrfs ~D,~D" crfD fpscrfS))))

;;; Move to Condition Register from XER

(define-ppc-op (mcrxr cr-field)
  (ppc/spr-move #b011111
                (assemble-fixnum (fx 3 cr-field) (0 0))
                0 0
                #b1000000000 0
                (lambda (port) (format port "mcrxr ~D" crfD))))

;;; Move from Condition Register

(define-ppc-op (mfcr rD)
  (ppc/spr-move #b011111
                (register-code rD)
                0 0
                #b0000010011 0
                (lambda (port) (format port "mfcr ~A" rD))))

;;; Move from FPSCR

(define-integrable (*mffs frD rc-bit)
  (ppc/spr-move #b111111
                (register-code frD)
                0 0
                #b1001000111 rc-bit
                (lambda (port)
                  (format port "mffs~A ~A"
                          (if (fx-zero? rc-bit) "" ".")
                          frD))))

(define-ppc-op (mffs  frD) (ppc/*mffs frD 0))
(define-ppc-op (mffs. frD) (ppc/*mffs frD 1))

;;; Move from Special-Purpose Register

(define-ppc-op (mfspr rD spr)
  (let ((code (register-code spr)))
    (ppc/spr-move #b011111
                  (register-code rD)
                  ;; Split the code into two fields.
                  (fx-and  code (fx-mask 5))
                  (fx-ashr code 5)
                  #b0101010011 0
                  (lambda (port)
                    (format port "mfspr ~A,~A" rD spr)))))

;;; Move from Time Base

(define-integrable (ppc/mftb rD u?)
  (ppc/spr-move #b011111
                (register-code rD)
                (assemble-fixnum (0 1 1 0) (bool u?))
                #b01000
                #b0101110011 0
                (lambda (port)
                  (format port "mftb~A ~A"
                          (if u? "u" "l")
                          rD))))

(define-ppc-op (mftbu rD) (ppc/mftb rD '#t))
(define-ppc-op (mftbl rD) (ppc/mftb rD '#f))

;;; Move to Condition Register Fields

(define-ppc-op (mtcrf cr-mask rS)
  (ppc/spr-move #b011111
                (register-code rS)
                (assemble-fixnum (0) (fx 4 4 cr-mask))
                (assemble-fixnum (fx 4 0 cr-mask) (0))
                #b0010010000 0
                (lambda (port)
                  (format port "mtcrf #b~B,~A" cr-mask rS))))

;;; Move to FPSCR Bit 0/1 (why not 'Set/Clear FPSCR Bit?')

(define-integrable (ppc/mtfsb crbD secondary n rc-bit)
  (ppc/spr-move #b111111
                crbD 0 0
                secondary rc-bit
                (lambda (port)
                  (format port "mtfsb~A~A ~D"
                          n
                          (if (fx-zero? rc-bit) "" ".")
                          crbD))))

(define-ppc-op (mtfsb0  crbD) (ppc/mtfsb crbD #b0001000110 0 0))
(define-ppc-op (mtfsb0. crbD) (ppc/mtfsb crbD #b0001000110 0 1))
(define-ppc-op (mtfsb1  crbD) (ppc/mtfsb crbD #b0000100110 1 0))
(define-ppc-op (mtfsb1. crbD) (ppc/mtfsb crbD #b0000100110 1 1))

;;; Move to FPSCR Fields

(define-integrable (ppc/*mtfsf field-mask frB rc-bit)
  (ppc/spr-move #b111111
                (assemble-fixnum (0) (fx 4 4 cr-mask))
                (assemble-fixnum (fx 4 0 cr-mask) (0))
                (register-code frB)
                #b1011000111 rc-bit
                (lambda (port)
                  (format port "mtfsf~A #b~B,~A"
                          (if (fx-zero? rc-bit) "" ".")
                          field-mask
                          frB))))

(define-ppc-op (mtfsf  field-mask frB) (ppc/*mtfsf field-mask frB 0))
(define-ppc-op (mtfsf. field-mask frB) (ppc/*mtfsf field-mask frB 1))

;;; Move to FPSCR Field Immediate

(define-integrable (ppc/*mtfsfi cr-field imm rc-bit)
  (ppc/spr-move #b111111
                (assemble-fixnum (fx 3 cr-field) (0 0))
                0
                (assemble-fixnum (fx 4 imm) (0))
                #b0010000110 rc-bit
                (lambda (port)
                  (format port "mtfsfi~A ~A,#b~B"
                          (if (fx-zero? rc-bit) "" ".")
                          cr-field
                          imm))))

(define-ppc-op (mtfsfi  cr-field imm) (ppc/*mtfsfi cr-field imm 0))
(define-ppc-op (mtfsfi. cr-field imm) (ppc/*mtfsfi cr-field imm 1))

;;; Move to Special-Purpose Register

(define-ppc-op (mtspr spr rS)
  (let ((code (register-code spr)))
    (ppc/spr-move #b011111
                  (register-code rS)
                  ;; Split the code into two fields.
                  (fx-and  code (fx-mask 5))
                  (fx-ashr code 5)
                  #b0111010011 0
                  (lambda (port)
                    (format port "mtspr ~A,~A" spr rS)))))